As the LSI is increased in size, an LSI including a plural number of macro cells, as functional blocks, mounted on a sole chip, has now been placed on the market. As such LSI, there has been known such an LSI which has a DRAM (dynamic random access memory) macro cell(s) and a logic macro cell(s) integrated on the same chip (see Patent Document 1).
In Patent Document 1, there is described a device including a plural number of dynamic random access memory (DRAM) macros 114, arranged in upper and lower parts of a chip, and a logic macro 116, inclusive of a memory controller 115, arranged between the upper and lower macros, at a mid part of the chip, as shown in FIG. 5. In an off-center position between the upper and lower macros, there is provided a clock signal generating circuit, specifically a PLL (phase locked loop) 112. An internal clock signal from the PLL is routed to the mid part of the chip and buffered in a buffer 113. It is then fanned out through a metal conductor to drive the macros and a logic core without clock skew. Specifically, the internal clock signal is generated by the PLL 112 provided at a rim part of the chip. The internal clock signal from the PLL is routed to the mid part of the chip, using a metal wire of a larger thickness and a large width (main clock line), in order to minimize the resistance/capacitance (RC) delay. The internal clock signal is then buffered in the buffer 113 and fanned out via a balanced inverter tree and a clock wire to drive the DRAM macros 114 and the logic macro 116. Near the mid part of the chip is arranged the memory controller 115 controlling the DRAM macros 114. On the rim part of the chip is arranged an I/O 111 including a plural number of input circuits for routing a signal received from outside to the inner part of the LSI chip and a plural number of output circuits for outputting signals from the inside to the outer side of the chip. The input circuits and the output circuits are connected to associated external terminals, not shown, provided in the I/O 111. It is through this I/O 111 that the clock signal is supplied to the PLL 112.
As the relevant technique, there is disclosed in Patent Document 2 a semiconductor integrated circuit device which, in connection with layout designing for a high-speed cache SRAM or a high performance micro-processor, for example, may suitably be employed for automatic location or interconnection employing a floor plan of the internal IO system.
[Patent Document 1]
JP Patent Kokai Publication No. JP-A-10-189889
[Patent Document 2]
JP Patent Kokai Publication No. JP-A-11-74465
[Non-Patent Document 3]
Simon Tam et al. “Clock Generation and Distribution for the 130-nm Itanium2 Processor with 6-MB On-Die L3 Cache”, IEEE JOURNAL OF SOLID-STATE CIRCUITS. VOL. 39, NO. 4, APRIL 2004, pp. 636-642